`timescale 1ns / 1ps

`define CBB_SIM


module tb ;
reg clk,rst_n;

//生成始时钟
parameter NCLK = 4;
initial begin
	clk=0;
	forever clk=#(NCLK/2) ~clk; 
end 


/****************** BEGIN ADD module inst ******************/
wire [1:0] o_dat ;
reg i_dat ;
initial begin
	i_dat <= 1'b0;
	repeat(100)begin
		@(posedge clk)begin 
			i_dat <= ~i_dat ;
		end 
		repeat(100) @(posedge clk) ;
	end
end
cbb_edge_detection u_edge_detection (clk,rst_n,i_dat , o_dat);

cbb_timer_ena  #(
    .N(32)
) u_cbb_timer_ena (
    .i_clk  ( clk), // 输入时钟
    .i_rst_n( rst_n), // 输入复位信号，低电平复位
    .i_times( 32'd52), // 计数值 
    .o_ena  ( )  // 计数时间到
) ;

cbb_dividers #(
	.ENABLE_SQUARE(0),
    .DIVISORS({32'd2, 32'd3, 32'd4 })  // 配置多个分频系数
) u_cbb_dividers (
    .i_clk(clk),
    .i_rst_n(rst_n),
    .o_clks() // 
); 

reg i_pulse ;
initial begin
	i_pulse = 1'b0 ;
	#100 ;
	@(posedge clk) ;
	@(posedge clk) 
		i_pulse = 1'b1 ;
	@(posedge clk) ;
	@(posedge clk) 
		i_pulse = 1'b0;
end

cbb_pulse_stretch #(
    .STRETCH_WIDTH  (4) // 展宽脉冲宽度
) u_cbb_pulse_stretch (
    .i_clk( clk),
    .i_rst_n( rst_n) ,
    .i_pulse( i_pulse) , 
    .o_pulse( )
);

/****************** BEGIN END module inst ******************/

initial begin
    $dumpfile("wave.lxt2");
    $dumpvars(0, tb);   //dumpvars(深度, 实例化模块1，实例化模块2，.....)
end

function integer clog2(input integer i);
    for(clog2=0;i>0 ; clog2=clog2+1)
        i=i>>1; 
endfunction 

initial begin
   	rst_n = 1;
    	#(NCLK) rst_n=0;
    	#(NCLK) rst_n=1; //复位信号

	repeat(1000) @(posedge clk)begin

	end
	$display($clog2(4) , clog2(4)) ;
	$display("运行结束！");
	$dumpflush;
	$finish;
	$stop;	
end 
endmodule
